1. Field of the Invention
This invention relates to the control of the impurity distribution within a semiconductor body, and more particularly relates to a novel control process for forming a wide range of predetermined impurity distributions.
2. Description of the Prior Art
The properties of semiconductor devices are determined in large measure by the profile of the impurity concentration within the semiconductor body. Impurities are introduced into the body by various mechanisms such as diffusion from gases, liquids or solids and ion implantation. Control of impurity concentration obtained by these processes has been limited since there are only two relationships previously known between the impurity concentration and the distance coordinate x below the surface of the semiconductor body. If an infinite source of impurities is provided at the semiconductor surface, the relation between impurity concentration n(x) at some depth x below the wafer is given by: ##EQU2##
Where erfc is the complementary function of error function (1-erf); and
T is time; and PA1 D is the diffusivity of the impurities.
The diffusivity D is in turn defined as ##EQU3##
Where .DELTA.E=activation energy, K=Boltzman's constant, and T is absolute temperature.
If a finite source is available on the semiconductor surface, then the impurity concentration at a distance (x) into the body of the semiconductor is given by: ##EQU4##
These concentration distributions are the only distributions available from presently available diffusion processes, and represent the generally exponentially decreasing concentration as a function of depth into the wafer surface shown in FIG. 1, for the wafer of FIG. 2. In FIG. 2, the wafer is shown schematically in cross-section and may be a monocrystalline silicon wafer with impurity atoms entering the top surface 10 of the wafer during diffusion. Other impurity concentration distributions, such as distributions which are hyperbolic or step-shaped in configuration, cannot now be predicted by the designer.
In order to obtain more complex impurity concentration profiles in devices, and to obtain a more pronounced "step" in the impurity concentration profile, designers have resorted to the epitaxial deposition of layers of one conductivity type or value on top of other conductivity layers. Epitaxial technology also allows a wide class of distribution functions n(x), but, as a rule, are less desirable than junctions formed by diffusion. Thus, to obtain a step-type impurity concentration profile of the type shown in FIG. 3, the designer might elect to epitaxially deposit an N-type layer 11 on a P-type wafer 12, as shown in FIG. 4, to produce the junction 13.
The use of an epitaxial layer in a semiconductor device is disadvantageous since the epitaxial layer has a degenerate crystal structure, as compared to bulk silicon (layer 12 in FIG. 4). Moreover, for high power semiconductor devices, where the recombination processes are essential, including high power diodes, thyristors, triacs and transistors, relatively thick epitaxial layers are needed at (for example, 4 mils), and these thicknesses are hard to make and are usually damaged and are less perfect than layers formed by the diffusion process.